1. Field of the Invention
The invention described pertains to the polishing methods and slurry formulations used in the planarization of integrated circuit surfaces containing various films, most particularly those of a metal, a barrier or liner layer, and a dielectric layer.
2. Related Art
One of the critical requirements necessary in the production of increasingly complex and dense semiconductor structures is the ability to retain planarity. Without the ability to planarize, the complexity and density of the structures constructed on a semiconductor wafer are greatly limited. Chemical-Mechanical Planarization, or CMP, is an enabling technology in this area, since it has proved to be the most effective method used to planarize surface films on semiconductor substrates.
While the first applications of CMP technology focused on the polishing of dielectric films (i.e., SiO2), polishing of metal structures used for circuit interconnects is increasing rapidly. Along with the increase in metal planarization is a inherent increase in the number of different films that are simultaneously polished. Most metal structures contain three different films: a conductive metal layer, a barrier (or liner) layer between the conductive metal layer and the adjacent dielectric layer, and a dielectric layer. It is often desirable for the removal rates of each film to differ from each other in order to induce planarity and maintain the integrity of the semiconductor structure during polishing. In a typical metal structure, for example, if the entire planarization step were to take place in one step of polishing, it would typically be desirable to have high removal rates of material for the metal and barrier layers, while having low removal rates for the dielectric layer.
However, while it is certainly desirable to limit the number of processing steps, there are often inherent difficulties associated with a one-step process that limit it""s usefullness. For example, copper interconnects, coupled with low-k dielectrics, have the potential (when compared to Al/SiO2) to increase chip speed, reduce the number of metal layers required, minimize power dissipation, and reduce manufacturing costs. A typical copper interconnect structure contains a conductive copper film, a barrier layer of tantalum or tantalum nitride, and a dielectric layer of silicon dioxide. In one-step copper CMP, it is desirable to remove the Cu and Ta/TaN barrier layer as fast as possible, while removing the SiO2 dielectric layer as slow as possible. However, this is often difficult, since the regimes in which Cu and Ta exhibit comparable removal rates often do not overlap. Also, it is critical to maintain the underlying semiconductor structure regardless of the removal rates of the various films. For the Cu CMP example, the removal of Cu within the interconnect features (called xe2x80x9cdishingxe2x80x9d or xe2x80x9crecessxe2x80x9d) is undesirable since optimal electrical performance is obtained when as much of the conducting metal line as possible remains. Also, it is also desirable to minimize the removal of the SiO2 dielectric layer within interconnect structures (called xe2x80x9cerosionxe2x80x9d).
To give satisfactory results in Cu CMP, Landers et al. in U.S. Pat. No. 5,676,587 have proposed a two-step polishing process to be used with Cu interconnect structures. The first step is designed to remove most of the overburden of Cu, and the second step is designed to remove the barrier or liner layer of Ta, TaN, Ti, or TiN. For the second step, a silica based slurry of near-neutral pH is detailed. However, U.S. Pat. No. 5,676,587 does not detail the specific removal rate requirements of the second step slurry. Farkas et al. in U.S. Pat. No. 5,773,364 presents the use of ammonium salts as oxidizers in metal CMP slurries. Farkas et al. in U.S. Pat. No. 5,614,444 discusses the use of materials with a polar and apolar component in silica-based slurries for the suppression of SiO2 removal rate during metal CMP processes. The use of quaternary ammonium salts as an example of a cationic compound is listed.
A method is provided for polishing a composite semiconductor structure containing a conducting metal interconnect layer, an insulating dielectric layer, and a barrier layer between the two: most preferably, a copper metal layer, a silicon dioxide dielectric layer, and a barrier layer of tantalum. The method involves a two-step polishing process: in the first step, the majority of the conducting metal layer is removed without removing significant amounts of either the barrier layer or the dielectric layer. In the second step, the metal interconnect remaining on the horizontal portions of the barrier layer and the barrier layer are removed without removing significant amounts of the dielectric layer, and without degrading the integrity of the remaining structure by significant removal of the remaining metal layer (commonly called xe2x80x9cdishingxe2x80x9d or xe2x80x9crecessxe2x80x9d) or removal of significant amounts of the remaining dielectric layer (commonly called xe2x80x9cerosionxe2x80x9d).
Preferred methods of the invention are:
a method for chemical-mechanical polishing of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer, wherein the method consists of the following steps:
a) removal of the majority of the metal layer using a first-step slurry that has high selectivity between the metal layer and the barrier layer;
b) removal of the barrier layer using a second-step slurry that has a high barrier removal rate, a low metal layer removal rate, a low dielectric layer removal rate and wherein the second-step slurry has a pH which is basic and, a method for chemical-mechanical polishing of a semiconductor structure comprised of a conductive metal interconnect layer, a barrier or liner film, and an underlying dielectric layer, wherein the method consists of the following steps:
a) removal of the majority of said metal layer using a first-step slurry that has high selectivity between said metal layer and said barrier layer;
b) removal of said barrier layer using a second-step slurry that has a high barrier removal rate, a metal layer removal rate between high and low, a low dielectric layer removal rate and wherein said second-step slurry has a pH which is basic.
An improved method of the CMP polishing of metal interconnect structures. This method is applicable to any metal interconnect structure containing: a conductive metal (such as Cu, Al, or W), a barrier or liner layer (such as Ta, TaN, Ti, or TiN), and an underlying ILD structure (such as SiO2 or a low-K dielectric). In the preferred embodiment, polishing of a structure containing a Cu layer, an underlying Ta barrier layer, and a SiO2 dielectric layer, using a two-step process is described. In the first step, the Cu overburden is removed while removing minimal amounts of the Ta liner or SiO2. The slurry used in the first step of this process is any slurry that can preferentially remove the copper metal overburden covering the semiconductor structure, and has very low rate of material removal on the Ta barrier layer and underlying SiO2 layer. Typically, this slurry would be alumina based, exhibit an acidic pH, and contain oxidizers that would enhance the chemical-mechanical removal of Cu at accelerated rates (above 2000 A/min). An example of a suitable first-step slurry is presented below.
For the second step, five different methods are described, each method depending on the state of the wafer after the first-step of polishing. The five methods discussed for second-step polishing of Cu interconnect structures can be summarized based on the removal rate and selectivity of each film (Table 1 and 2). It should be noted that the slurries maintaining the selectivities in Table 2 but having different removal rates as described in Table 1 would also be suitable and appropriate in this application.
Method 1xe2x80x94This method utilizes a slurry with significant ( greater than 1000 A/min) removal rates of Ta and Cu, and low removal rates of oxide. This method can be used when significant amounts of Cu remain after first step polishing on portions of the wafer. By having high removal rates of both Cu and Ta, any remaining Cu can be removed during removal of the Ta barrier layer. Low removal rates of SiO2 minimizes the amount of oxide erosion.
Method 2xe2x80x94This method utilizes a slurry with significant removal rates of Ta, but low removal rates of Cu and SiO2. This method should be used when very little Cu overburden remains after first-step polishing. This allows for rapid and complete removal of the Ta barrier layer, with little removal of the Cu interconnect structures or the underlying SiO2 dielectric.
Method 3xe2x80x94This method utilizes a slurry with significant removal rates of Ta, somewhat lower removal rates of Cu, and low removal rates of SiO2. This method should be used when some Cu overburden remains, but not as much as was observed under Method 1. This allows for the removal of any Cu remaining on the wafer, complete and rapid removal of the Ta barrier layer, and little removal of the underlying SiO2 layer.
Method 4xe2x80x94This method utilizes a slurry with significant removal rates of Ta, somewhat lower removal rates of Cu, and somewhat lower removal rates of SiO2. This method should be used when some Cu overburden remains, as was discussed in Method 3. Also, this method is effective in removal of some of the underlying SiO2 dielectric layer, which helps to decrease the amount of dishing of the adjacent Cu structures, as well as improving the quality of the SiO2 surface (by xe2x80x9ctouching-upxe2x80x9d or xe2x80x9cbuffingxe2x80x9d this surface). This allows for the removal of any Cu remaining on the wafer, complete and rapid removal of the Ta barrier layer, and some removal of the underlying SiO2 layer to lower dishing and improve surface quality.
Method 5xe2x80x94This method utilizes a slurry with significant and similar removal rates of Ta, Cu, and SiO2. Since this method can retain planarity due to equivalent removal rates, it can be used in any case when the surface produced after first step polishing is planar or nearly planar (i.e., when no Cu dishing or recess is observed). This method allows for the removal of any residual Cu overburden, the Ta barrier layer, and improvement of the underlying SiO2 layer (as discussed in Method 4).
With the proper application of the above methods, patterned semiconductor wafers can be produced with low observed dishing or recess of the interconnect structures (in particular, Cu) as well as low erosion of the underlying dielectric layer (i.e., SiO2). One important benefit of this method is that, by adjusting the second step slurry to compensate for any deficiencies generated in the first step of polishing, a more robust process capable of generating improved polishing results is developed. It has been determined that, through the addition of certain additives in specific amounts, the removal rates of Cu, Ta, and SiO2 can be controlled in order to produce the removal rates described in the five methods discussed above.
In each method, a Ta removal rate above 1000 A/min is desired. Removal of Ta is enhanced at in alkaline pH ranges: therefore, all slurries discussed are in a pH range above 7. Silica is used as the mechanical portion of the slurries listed below: however, any metal oxide (e.g., alumina, titania, zirconia, etc.) or abrasive particles with suitably low particle size ( less than 1 micron) would be appropriate for this application.
In the methods described above, the Cu removal rate ranges from under 250 A/min to over 1000 A/min. Benzotriazole, or BTA, is a well known passivating agent for Cu, and has been demonstrated to be effective in inhibiting Cu removal rates during CMP polishing (Steigerwald, 1995). By the addition of BTA is small amounts (between 0.0 and 0.06 wt. %), the Cu RR can be controlled within this range.
In the methods described above, the removal rate of SiO2 varies from less than 100 A/min to over 1000 A/min, with most methods having lower removal rates. It is easy to achieve removal rates above 1000 A/min for SiO2 films at alkaline conditions: commercially available products such as Rodel ILD 1200 (KOH based) and ILD 1300 (NH4OH based) easily produce removal rates above 1000 A/min for ILD films. The use of compounds containing quaternary ammonium cations enables the use of an alkaline slurry with lower SiO2 removal rates. The use of quaternary ammonium compounds as oxide suppressants has been discussed in U.S. Pat. No. 5,614,444. However, it is found below that the effectiveness with respect to oxide suppression of the quaternary ammonium compound is enhanced when another quaternary ammonium compound, namely ammonium hydroxide, is present in the slurry. Removal rates for SiO2 of  less than 100 A/min were most easily achieved through the use of two quaternary ammonium compounds.